View AD1886_166632.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

a
AC'97 2.1 FEATURES Variable Sample Rate Audio Multiple Codec Configuration Options External Audio Power-Down Control AC'97 FEATURES AC'97 2.2 Compliant Greater than 90 dB Dynamic Range Stereo Headphone Amplifier Multibit - Converter Architecture for Improved S/N Ratio Greater than 90 dB 16-Bit Stereo Full-Duplex Codec Four Analog Line-Level Stereo Inputs for: LINE-IN, CD, VIDEO, and AUX Two Analog Line-Level Mono Inputs for Speakerphone and PC BEEP Mono MIC Input w/Built-In 20 dB Preamp, Switchable from Two External Sources High-Quality CD Input with Ground Sense
AC'97 SoundMAX Codec AD1886A
(R)
Stereo Line Level Outputs Mono Output for Speakerphone or Internal Speaker Power Management Support 48-Terminal LQFP Package ENHANCED FEATURES 20-Bit SPDIF Output w/32 kHz, 44.1 kHz, and 48 kHz Symbol Rates Full Duplex Variable Sample Rates from 7040 Hz to 48 kHz with 1 Hz Resolution Jack Sense Pins Provide Automatic Output Switching Software-Enabled VREFOUT Output for Microphones and External Power Amp Split Power Supplies (3.3 V Digital/5 V Analog) Mobile Low-Power Mixer Mode Extended 6-Bit Master Volume Control Extended 6-Bit Headphone Volume Control Digital Audio Mixer Mode PhatTM Stereo 3D Stereo Enhancement
FUNCTIONAL BLOCK DIAGRAM
ID0 ID1 JS SPDIF
VREFOUT MIC1 MIC2 LINE AUX CD VIDEO PHONE_IN 0dB/ 20dB
VREF CHIP SELECT JACK SENSE
AD1886A
SPDIF OUT
SELECTOR
PGA
16-BIT - A/D CONVERTER
PGA
16-BIT - A/D CONVERTER
RESET
SYNC MONO_OUT MV G A M G A M G A M G A M G A M G A M G A M
AC LINK
SAMPLE RATE GENERATORS
BIT_CLK
HP_OUT_L
MV
PHAT STEREO
SDATA_OUT 16-BIT - D/A CONVERTER
LINE_OUT_L
MV
SDATA_IN
LINE_OUT_R
MV
PHAT STEREO A M G = GAIN A = ATTENUATE M = MUTE
G A M
16-BIT - D/A CONVERTER
HP_OUT_R
MV
OSCILLATOR
PC_BEEP
XTAL_OUT XTAL_IN
SoundMAX is a registered trademark and Phat is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
AD1886A-SPECIFICATIONS
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED Temperature Digital Supply (VDD) Analog Supply (VCC) Sample Rate (fS) Input Signal Analog Output Pass Band VIH VIL VIH (CS0, CS1, CHAIN_IN) VIL
ANALOG INPUT
25C 3.3 V 5.0 V 48 kHz 1008 Hz 20 Hz to 20 kHz 2.0 V 0.8 V 4.0 V 1.0 V
DAC Test Conditions Calibrated -3 dB Attenuation Relative to Full Scale Input 0 dB 10 k Output Load (LINE_OUT) 32 Output Load (HP_OUT) ADC Test Conditions Calibrated 0 dB Gain Input -3.0 dB Relative to Full Scale
Parameter Input Voltage (RMS Values Assume Sine Wave Input) LINE_IN, AUX, CD, VIDEO, PHONE_IN, PC_BEEP MIC1 or MIC2 with +20 dB Gain (M20 = 1) MIC1 or MIC2 with 0 dB Gain (M20 = 0) Input Impedance* Input Capacitance*
MASTER VOLUME
Min
Typ 1 2.83 0.1 0.283 1 2.83 20 5
Max
Unit V rms V p-p V rms V p-p V rms V p-p k pF
7.5
Parameter Step Size (0 dB to -94.5 dB); LINE_OUT_L, LINE_OUT_R Output Attenuation Range Span* Step Size (0 dB to -46.5 dB); MONO_OUT Output Attenuation Range Span* Step Size (+6 dB to -88.5 dB); HP_OUT_R, HP_OUT_L Output Attenuation Range Span* Mute Attenuation of 0 dB Fundamental*
PROGRAMMABLE GAIN AMPLIFIER--ADC
Min
Typ 1.5 -94.5 1.5 -46.5 1.5 -94.5
Max
Unit dB dB dB dB dB dB dB
80
Parameter Step Size (0 dB to 22.5 dB) PGA Gain Range Span
ANALOG MIXER--INPUT GAIN / AMPLIFIERS / ATTENUATORS
Min
Typ 1.5 22.5
Max
Unit dB dB
Parameter Signal-to-Noise Ratio (SNR) CD to LINE_OUT Other to LINE_OUT Step Size (+12 dB to -34.5 dB): (All Steps Tested) MIC, LINE_IN, AUX, CD, VIDEO, PHONE_IN, DAC Input Gain/Attenuation Range: MIC, LINE, AUX, CD, VIDEO, PHONE_IN, DAC Step Size (0 dB to -45 dB): (All Steps Tested) PC_BEEP Input Gain/Attenuation Range: PC_BEEP
*Guaranteed but not tested.
Min
Typ 90 90 1.5 -46.5 3.0 -45
Max
Unit dB dB dB dB dB dB
-2-
REV. 0
AD1886A
DIGITAL DECIMATION AND INTERPOLATION FILTERS*
Parameter Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Rejection Group Delay Group Delay Variation over Pass Band
ANALOG-TO-DIGITAL CONVERTERS
Min 0 0.4 x fS 0.6 x fS -74
Typ
Max 0.4 x fS 0.09 0.6 x fS 12/fS 0.0
Unit Hz dB Hz Hz dB sec s
Parameter Resolution Total Harmonic Distortion (THD) Dynamic Range (-60 dB input THD + N Referenced to Full Scale, A-Weighted) Signal-to-Intermodulation Distortion* (CCIF Method) ADC Crosstalk* Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) LINE_IN to Other Gain Error (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) ADC Offset Error
DIGITAL-TO-ANALOG CONVERTERS
Min
Typ 16 -84 87 85 -100 -90
Max
Unit Bits dB dB dB
84
-90 -85 10 0.5 5
dB dB % dB mV
Parameter Resolution Total Harmonic Distortion (THD) LINE_OUT Total Harmonic Distortion (THD) HP_OUT Dynamic Range (-60 dB Input THD + N Referenced to Full Scale, A-Weighted) Signal-to-Intermodulation Distortion* (CCIF Method) Gain Error (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) DAC Crosstalk* (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT) Total Audible Out-of-Band Energy (Measured from 0.6 x fS to 20 kHz)*
ANALOG OUTPUT
Min
Typ 16 -85 -75 90 -100 10
Max
Unit Bits dB dB dB dB % dB dB dB
85
0.7 -80
-40
Parameter Full-Scale Output Voltage; LINE_OUT Output Impedance* External Load Impedance* Output Capacitance* External Load Capacitance Full-Scale Output Voltage; HP_OUT (0 dB Gain) Output Capacitance* External Load Impedance* VREF VREF_OUT VREF _OUT Current Drive Mute Click (Muted Output Minus Unmuted Midscale DAC Output)
*Guaranteed but not tested.
Min
Typ 1 2.83
Max
Unit V rms V p-p k pF pF V rms pF V V mA mV
800 10 15 100 1 100 32 2.05 2.25 2.25 5 2.45 5
REV. 0
-3-
AD1886A-SPECIFICATIONS
STATIC DIGITAL SPECIFICATIONS
Parameter High-Level Input Voltage (VIH): Digital Inputs Low-Level Input Voltage (VIL) High-Level Output Voltage (VOH), IOH = 2 mA Low-Level Output Voltage (VOL), IOL = 2 mA Input Leakage Current Output Leakage Current
POWER SUPPLY
Min 0.65 x DVDD 0.9 x DVDD -10 -10
Typ
Max 0.35 x DVDD 0.1 x DVDD +10 +10
Unit V V V V A A
Parameter Power Supply Range--Analog (AVDD) Power Supply Range--Digital (DVDD) Power Dissipation--5 V/3.3 V Analog Supply Current--5 V (AVDD) Digital Supply Current--3.3 V (DVDD) Power Supply Rejection (100 mV p-p Signal @ 1 kHz)* (At Both Analog and Digital Supply Pins, Both ADCs and DACs)
CLOCK SPECIFICATIONS*
Min 4.75 3.0
Typ 5.0 3.3 306 48 20 40
Max 5.25 3.6
Unit V V mW mA mA dB
Parameter Input Clock Frequency Recommended Clock Duty Cycle
POWER-DOWN STATES
Min 40
Typ 24.576 50
Max 60
Unit MHz %
Parameter ADC DAC ADC + DAC ADC + DAC + Mixer (Analog CD On) Mixer ADC + Mixer DAC + Mixer ADC + DAC + Mixer Analog CD Only (AC-Link On) Analog CD Only (AC-Link Off) Standby Headphone Standby
*Guaranteed but not tested. Specifications subject to change without notice.
Set Bits PR0 PR1 PR1, PR0 LPMIX, PR1, PR0 PR2 PR2, PR0 PR2, PR1 PR2, PR1, PR0 LPMIX, PR5, PR1, PR0 LPMIX, PR1, PR0, PR4, PR5 PR5, PR4, PR3, PR2, PR1, PR0 PR6
DVDD Typ 17.5 17.0 4.1 4.1 20 17.6 17 4.1 4.1 0 0 20
AVDD Typ 41.6 38.3 31.9 22.4 17.5 11.2 8.4 2.2 22.4 22.4 0 38.8
Unit mA mA mA mA mA mA mA mA mA mA mA mA
-4-
REV. 0
AD1886A
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Parameter RESET Active Low Pulsewidth RESET Inactive to BIT_CLK Startup Delay SYNC Active High Pulsewidth SYNC Low Pulsewidth SYNC Inactive to BIT_CLK Startup Delay BIT_CLK Frequency BIT_CLK Period BIT_CLK Output Jitter* BIT_CLK High Pulsewidth BIT_CLK Low Pulsewidth SYNC Frequency SYNC Period Setup to Falling Edge of BIT_CLK Hold from Falling Edge of BIT_CLK BIT_CLK Rise Time BIT_CLK Fall Time SYNC Rise Time SYNC Fall Time SDATA_IN Rise Time SDATA_IN Fall Time SDATA_OUT Rise Time SDATA_OUT Fall Time End of Slot 2 to BIT_CLK, SDATA_IN Low Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT) Rising Edge of RESET to HI-Z Delay Propagation Delay RESET Rise Time Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid
*Guaranteed but not tested. Specifications subject to change without notice.
Symbol tRST_LOW tRST2CLK tSYNC_HIGH tSYNC_LOW tSYNC2CLK tCLK_PERIOD tCLK_HIGH tCLK_LOW tSYNC_PERIOD tSETUP tHOLD tRISECLK tFALLCLK tRISESYNC tFALLSYNC tRISEDIN tFALLDIN tRISEDOUT tFALLDOUT tS2_PDOWN tSETUP2RST tOFF
Min 162.8
Typ 1.0 1.3 19.5
Max
Unit s ns ms s ns MHz ns ps ns ns kHz s ns ns ns ns ns ns ns ns ns ns s ns ns ns ns ns
162.8 12.288 81.4 32.56 32.56 42 38 48.0 20.8 2.5 4 4 4 4 4 4 4 4 750 48.84 48.84
5 5 2 2 2 2 2 2 2 2 0 15
6 6 6 6 6 6 6 6 1.0 25 15 50 15
REV. 0
-5-
AD1886A
tRST_LOW
RESET
tRST2CLK
BIT_CLK
tRISECLK
SYNC
tFALLCLK
BIT_CLK
Figure 1. Cold Reset
tRISESYNC
SDATA_IN
tFALLSYNC
tSYNC_HIGH
SYNC
tRST2CLK
SDATA_OUT
tRISEDIN
tFALLDIN
BIT_CLK
tRISEDOUT
tFALLDOUT
Figure 2. Warm Reset
tCLK_LOW
BIT_CLK
Figure 5. Signal Rise and Fall Time
tCLK_HIGH tCLK_PERIOD
SYNC
SLOT 1
SLOT 2
BIT_CLK
tSYNC_LOW
SYNC
SDATA_OUT
WRITE TO 0x26
DATA PR4
DON'T CARE
tSYNC_HIGH tSYNC_PERIOD
tS2_PDOWN
SDATA_IN NOTE: BIT_CLK NOT TO SCALE
Figure 3. Clock Timing
Figure 6. AC Link Low Power Mode Timing
tSETUP
RESET
BIT_CLK SYNC SDATA_OUT
SDATA_OUT
tSETUP2RST
SDATA_IN, BIT_CLK HI-Z
tHOLD
tOFF
Figure 4. Data Setup and Hold
Figure 7. ATE Test Mode
-6-
REV. 0
AD1886A
ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE
Parameter Power Supplies Digital (DVDD) Analog (AVCC) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Ambient Temperature (Operating) Storage Temperature
Min -0.3 -0.3 -0.3 -0.3 0 -65
Max +3.6 +6.0 10.0 AVDD + 0.3 DVDD + 0.3 70 +150
Unit Model V V mA V V C C
Temperature Range
Package Description 48-Lead LQFP
Package Option* ST-48
AD1886AJST 0C to 70C
*ST = Thin Quad Flatpack.
ENVIRONMENTAL CONDITIONS
*Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Ambient Temperature Rating TAMB = TCASE - (PD x CA) TCASE = Case Temperature in C PD = Power Dissipation in W CA = Thermal Resistance (Case-to-Ambient) JA = Thermal Resistance (Junction-to-Ambient) JC = Thermal Resistance (Junction-to-Case) Package LQFP
JA JC CA
76.2C/W
17C/W
59.2C/W
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1886A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
-7-
AD1886A
PIN CONFIGURATION
HP_OUT_R HP_OUT_L MONO_OUT
36 35 34 33 32
SPDIF
AVDD3
48 47 46 45 44 43 42 41 40 39 38 37
DVDD1 1 XTL_IN 2 XTL_OUT 3 DVSS1 4 SDATA_OUT 5 BIT_CLK 6 DVSS2 7 SDATA_IN 8 DVDD2 9 SYNC 10 RESET 11 PC_BEEP 12
AVDD2
ID0 AVSS3
AVSS2
ID1
NC
JS
PIN 1 IDENTIFIER
LINE_OUT_R LINE_OUT_L CX3D RX3D FILT_L FILT_R AFILT2 AFILT1 VREFOUT VREF AVSS1 AVDD1
AD1886A
TOP VIEW (Not to Scale)
31 30 29 28 27 26 25
13 14 15 16 17 18 19 20 21 22 23 24
CD_GND_REF
LINE_IN_L
PHONE_IN
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS Digital I/O
Pin Name XTL_IN XTL_OUT SDATA_OUT BIT_CLK SDATA_IN SYNC RESET SPDIF
CHIP SELECTS
LQFP 2 3 5 6 8 10 11 48
I/O I O I O/I O I I O
Description Crystal (or Clock) Input, 24.576 MHz. Crystal Output AC-Link Serial Data Output, AD1886A Input Stream. AC-Link Bit Clock. 12.288 MHz Serial Data Clock. Daisy-Chain Output Clock. AC-Link Serial Data Input. AD1886A Output Stream. AC-Link Frame Sync AC-Link Reset. AD1886A Master H/W Reset. SPDIF Output
Pin Name ID0 ID1
LQFP 45 46
Type I I
Description Chip Select Input 0 (Active Low) Chip Select Input 1 (Active Low)
JACK SENSE/GENERAL-PURPOSE DIGITAL OUTPUT
The JS pin can be used to sense the presence of an audio plug in the output jacks and automatically mute the MONO and/or LINE_OUT audio outputs. Alternatively, the JS can be programmed as a general-purpose digital output pin. Pin Name JS LQFP 47 Type I/O Description JACK SENSE Input, or GPIO.
-8-
LINE_IN_R
AUX_L
AUX_R
CD_L
CD_R
MIC1
VIDEO_L
VIDEO_R
MIC2
REV. 0
AD1886A
Analog I/O
These signals connect the AD1886A component to analog sources and sinks, including microphones and speakers. Pin Name PC_BEEP PHONE AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND_REF CD_ R MIC1 MIC2 LINE_IN_L LINE_IN_R LINE_OUT_L LINE_OUT_R MONO_OUT HP_OUT_L HP_OUT_R
Filter/Reference
LQFP 12 13 14 15 16 17 18 19 20 21 22 23 24 35 36 37 39 41
I/O I I I I I I I I I I I I I O O O O O
Description PC Beep. PC Speaker beep passthrough. Phone. From telephony subsystem speakerphone or handset. Auxiliary Input Left Channel Auxiliary Input Right Channel Video Audio Left Channel Video Audio Right Channel CD Audio Left Channel CD Audio Analog Ground Reference for CD Input CD Audio Right Channel Microphone 1. Desktop microphone input. Microphone 2. Second microphone input. Line In, Left Channel. Line In, Right Channel. Line Out, Left Channel. Line Out, Right Channel. Monaural Output to Telephony Subsystem Speakerphone Headphones Out, Left Channel. Headphones Out, Right Channel.
These signals are connected to resistors, capacitors, or specific voltages. Pin Name VREF VREFOUT AFILT1 AFLIT2 FILT_R FILT_L RX3D CX3D LQFP 27 28 29 30 31 32 33 34 I/O O O O O O O O I Description Voltage Reference Filter Voltage Reference Output 5 mA Drive. (Intended for Mic Bias.) Antialiasing Filter Capacitor--ADC Right Channel. Antialiasing Filter Capacitor--ADC Left Channel. AC-Coupling Filter Capacitor--ADC Right Channel. AC-Coupling Filter Capacitor--ADC Left Channel. 3D Phat Stereo Enhancement--Resistor. 3D Phat Stereo Enhancement--Capacitor.
Power and Ground Signals
Pin Name DVDD1 DVSS1 DV SS2 DVDD2 AVDD1 AVSS1 AVDD2 AVSS2 AVDD3 AVSS3
No Connects
LQFP 1 4 7 9 25 26 38 40 43 44
Type I I I I I I I I I I
Description Digital VDD 3.3 V Digital GND Digital GND Digital VDD 3.3 V Analog VDD 5.0 V Analog GND Analog VDD 5.0 V Analog GND Analog VDD 5.0 V Analog GND
Pin Name NC
LQFP 42
Type
Description No Connect
REV. 0
-9-
AD1886A
JS SPDIF
AD1886A
MIC1 MIC2
SPDIF JACK SENSE 0x72 0x3A 0x2A 0x28 0x72
0 MS 1 S 0x20
0dB/20dB M20 0x0E
LS/RS (0) LS (4) RS (4) GM 0x1C LIM LS (3) S IM RS (3) E L LS (1) E RS (1) C T LS (2) O RS (2) R LS/RS (7) GM 0x1C RIM LS (5) IM LS/RS (6) RS (5)
LINE_IN
AUX CD
GM 0x1C LIV IM
16-BIT - A/D
VIDEO PHONE_IN
GM 0x1C RIV IM
16-BIT - A/D
RESET
S 0x1A
SYNC GA 0x0C PHV M 0x0C PHM 0x04 0x04 LHV A 0x02 LMV A 0x06 MMV A 0x02 RMV 0x04 RHV M 0x0A PCM GAM 0x18 LOV OM M 0x0E MCM M 0x10 LM M 0x12 CM M 0x16 AM M 0x14 VM SDATA_IN GA 0x0E GA 0x10 MCV LLV RLA GA 0x12 LCV RCV GA 0x16 LAV RAV GA 0x14 LVV RVV
AC LINK
BIT_CLK
SDATA_OUT
HP_OUT_L
HPM M 0x02
LINE_OUT_L
MM M 0x06
3D 0x22 POP3D
16-BIT - D/A
MIX 0 1 S 0x20
D A M 3D 0x22 POP3D
MONO_OUT MMM M 0x02 MM 0x04
3D 0x20 SWITCH
LINE_OUT_R
GAM 0x18 ROV OM
16-BIT - D/A
HP_OUT_R
HPM
PC_BEEP
A 0x0A PCV
OSCILLATORS
XTL_OUT
XTL_IN
Figure 8. Block Diagram Register Map
-10-
REV. 0
AD1886A
Indexed Control Registers
Reg Num
00h 02h 04h 06h 08h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 20h 22h 26h 28h 2Ah Name Reset Master Volume Headphones Volume Master Volume Mono Reserved PC Beep Volume Phone-In Volume Mic Volume Line-In Volume CD Volume Video Volume Aux Volume PCM Out Vol Record Select Record Gain General-Purpose 3D Control Power-Down Ctrl/Stat Ext'd Audio ID Ext'd Audio Stat/Ctrl D15 X MM HPM MMM X PCM PHM MCM LM CVM VM AM OM X IM POP X X ID1 X D14 SE4 X X X X X X X X X X X X X X X X X ID0 X SR14 D13 SE3 LMV5 LHV5 X X X X X X X X X X X X 3D X PR5 X X SR13 D12 SE2 LMV4 LHV4 X X X X X LLV4 LCV4 LVV4 LAV4 LOV4 X X X X PR4 X X SR12 D11 SE1 LMV3 LHV3 X X X X X LLV3 LCV3 LVV3 LAV3 LOV3 X LIM3 X X PR3 X X SR11 D10 SE0 D9 ID9 D8 ID8 D7 ID7 D6 ID6 X X X X X X M20 X X X X X X X D5 ID5 D4 ID4 D3 ID3 RMV3 RHV3 MMV3 X PCV2 PHV3 MCV3 RLV3 RCV3 RVV3 RAV3 ROV3 X RIM3 X DP3 REF X X SR3 D2 ID2 RMV2 RHV2 D1 ID1 D0 ID0 Default 0410h 8000h 8000h
LMV2 LMV1 LMV0 X LHV2 X X X X X LLV2 LCV2 LVV2 LAV2 LOV2 LS2 LIM2 X X PR2 X SPCV SR10 LHV1 X X X X X LLV1 LCV1 LVV1 LAV1 LOV1 LS1 LIM1 MIX X PR1 X X SR9 LHV0 X X X X X LLV0 LCV0 LVV0 LAV0 LOV0 LS0 LIM0 MS X PR0 X X SR8 X X X X X X X X X X X X X
RMV5 RMV4 RHV5 X X X X X X X X X X X X X X X X RHV4 MMV4 X PCV3 PHV4 MCV4 RLV4 RCV4 RVV4 RAV4 ROV4 X X X X X X
RMV1 RMV0 RHV1 RHV0
MMV2 MMV1 MMV0 8000h X PCV1 PHV2 MCV2 RLV2 RCV2 RVV2 RAV2 ROV2 RS2 RIM2 X DP2 ANL SPDF X PCV0 X X X 8000h 8008h 8008h 8808h 8808h 8808h 8808h 8808h 0000h 8000h 0000h 0000h 000Xh 0005h 0000h BB80h
PHV1 PHV0 MCV1 MCV0 RLV1 RLV0
RCV1 RCV0 RVV1 RVV0
RAV1 RAV0 ROV1 ROV0 RS1 RIM1 X DP1 DAC X RS0 RIM0 X DP0 ADC VRA VRA SR0
LPBK X X X X X SR7 X X X X SR6
SPSA1 SPSA0 SR5 SR4
SPDIF X SR2 SR1
2Ch/ PCM DAC Rate (SR1) SR15 (7Ah)* 32h/ PCM ADC Rate (SR0) SR15 (78h)* 3Ah 72h 74h 76h SPDIF Control Jack Sense/SPDIF Serial Configuration Misc Control Bits V SPMIX
SR14
SR13
SR12
SR11
SR10
SR9
SR8
SR7
SR6
SR5
SR4
SR3
SR2
SR1 AUD JS0 X X
SR0
BB80h
X JSOD
SPSR1 SPRZ
SPSR0 JSPD
L X
CC6 JSOE
CC5 JSLM X X
CC4 JSD X ALSR
CC3 X X
CC2 JSC X
CC1
CC0
PRE VWI X X
COPY JS1 X DRSR
PRO JSI X ARSR
0000h 0000h 7000h 0404h
JSMM JSM X SRX8 D7 S5 REV5 X X
SLOT16 REGM2 REGM1 REGM0 DRQEN X DACZ LPMIX X DAM DMS DLSR
MOD SRX1 EN 0D7 S7 S6
7Ch 7Eh
Vendor ID1 Vendor ID2
F7 T7
F6 T6
F5 T5
F4 T4
F3 T3
F2 T2
F1 T1
F0 T0
S4 REV4
S3 REV3
S2 REV2
S1 REV1
S0 REV0
4144h 5363h
REV7 REV6
NOTES All registers not shown and bits containing an X are assumed to be reserved. Odd register addresses are aliased to the next lower even address. Reserved registers should not be written. Zeros should be written to reserved bits. *Indicates Aliased register for AD1819, AD1819A backward compatibility
REV. 0
-11-
AD1886A
Reset (Index 00h)
Reg Name Num 00h Reset D15 X D14 SE4 D13 SE3 D12 SE2 D11 SE1 D10 SE0 D9 D9 ID9 D8 D8 ID8 D7 D7 ID7 D6 D6 ID6 D5 D5 ID5 D4 D4 ID4 D3 D3 ID3 D2 D2 ID2 D1 D1 ID1 D0 D0 ID0 Default 0410h
Note: Writing any value to this register performs a register reset, which causes all registers to revert to their default values (except 74h, which forces the serial configuration). Reading this register returns the ID code of the part and a code for the type of 3D Stereo Enhancement. ID[9:0] Identify Capability. The ID decodes the capabilities of AD1886A based on the following: Bit = 1 ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9 SE[4:0]
Reg Num 02h
Function Dedicated Mic PCM in Channel Modem Line Codec support Bass and Treble Control Simulated Stereo (Mono to Stereo) Headphone Out Support Loudness (Bass Boost) Support 18-Bit DAC Resolution 20-Bit DAC Resolution 18-Bit ADC Resolution 20-Bit ADC Resolution
AD1886A* 0 0 0 0 1 0 0 0 0 0
*The AD1886A contains none of the optional features identified by these bits.
Stereo Enhancement. The 3D stereo enhancement identifies the Analog Devices 3D stereo enhancement.
Master Volume Registers (Index 02h)
Name Master Volume D15 MM MM D14 X D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 X D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
LMV5 LMV4 LMV3 LMV2 LMV1 LMV0 X
RMV5 RMV4 RMV3 RMV2 RMV1 RMV0 8000h
RMV[5:0] LMV[5:0] MM
Right Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of -94.5 dB. Left Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of -94.5 dB. Master Volume Mute. When this bit is set to "1," the channel is muted. MM 0 0 0 1 xMV5 . . . xMV0 00 0000 01 1111 11 1111 xx xxxx Function 0 dB Attenuation -46.5 dB Attenuation -94.5 dB Attenuation - dB Attenuation
-12-
REV. 0
AD1886A
Headphones Volume Registers (Index 04h)
Reg Num 04h Name Headphone Volume D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 LHV5 LHV4 LHV3 LHV2 LHV1 LHV0 X HPM X D6 D6 X D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default RHV5 RHV4 RHV3 RHV2 RHV1 RHV0 8000h
RHV[5:0] LHV[5:0] HPM
Right Headphone Volume Control. The least significant bit represents 1.5 dB. This register controls the output from +6 dB to a maximum attenuation of -88.5 dB. Left Headphone Volume Control. The least significant bit represents 1.5 dB. This register controls the output from +6 dB to a maximum attenuation of -88.5 dB. Headphones Volume Mute. When this bit is set to "1," the channel is muted. HPM 0 0 0 1 xHV5 . . . xHV0 00 0000 01 1111 11 1111 xx xxxx Function 6 dB Gain -40.5 dB Attenuation -88.5 dB Attenuation - dB Attenuation
Master Volume Mono (Index 06h)
Reg Num 06h Name D15 D14 D13 D12 D11 D10 D9 D9 Master Volume Mono MMM X X X X X X D8 D8 X D7 D7 X D6 D6 X D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
MMV5 MMV4 MMV3 MMV2 MMV1 MMV0 8000h
MMV[5:0] MMM
Reg Num 0Ah
Mono Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of -94.5 dB. Mono Master Volume Mute. When this bit is set to "1," the channel is muted.
PC Beep Register (Index 0Ah)
Name PC_BEEP Volume D15 PCM D14 X D13 X D12 X D11 X D10 X D9 D9 X D8 D8 X D7 D7 X D6 D6 X D5 D5 X D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default 8000h
PCV3 PCV2 PCV1 PCV0 X
PCV[3:0]
PC Beep Volume Control. The least significant bit represents 3 dB attenuation. This register controls the output from 0 dB to a maximum attenuation of -45 dB. The PC Beep is routed to Left and Right Line outputs even when AD1886A is in a RESET State. This is so Power-On Self-Test (POST) codes can be heard by the user in case of a hardware problem with the PC. PC Beep Mute. When this bit is set to "1," the channel is muted. PCM 0 0 1 PCV3 . . . PCV0 0000 1111 xxxx Function 0 dB Attenuation 45 dB Attenuation dB Attenuation
PCM
REV. 0
-13-
AD1886A
Phone Volume (Index 0Ch)
Reg Num 0Ch Name Phone Volume D15 PHM D14 X D13 X D12 X D11 X D10 X D9 D9 X D8 D8 X D7 D7 X D6 D6 X D5 D5 X D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
PHV4 PHV3 PHV2 PHV1 PHV0 8008h
PHV[4:0] PHM
Reg Name Num 0Eh MIC Volume
Phone Volume. Allows setting the Phone Volume Attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Phone Mute. When this bit is set to "1," the channel is muted.
Mic Volume (Index 0Eh)
D15 D14 D13 X D12 X D11 X D10 X D9 D9 X D8 D8 X D7 D7 X D6 D6 M20 D5 D5 X D4 D4 MCV4 D3 D3 MCV3 D2 D2 MCV2 D1 D1 MCV1 D0 D0 MCV0 Default 8008h
MCM X
MCV[4:0] M20
Mic Volume Gain. Allows setting the Mic Volume attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Microphone 20 dB Gain Block 0 = Disabled; Gain = 0 dB 1 = Enabled; Gain = 20 dB Mic Mute. When this bit is set to "1," the channel is muted.
MCM
Reg Name Num 10h
Line In Volume (Index 10h)
D15 D14 D13 D12 X X D11 D10 D9 D9 D8 D8 D7 D7 X D6 D6 X D5 D5 X D4 D4 RLV4 D3 D3 RLV3 D2 D2 RLV2 D1 D1 RLV1 D0 D0 RLV0 Default 8808h
LM Line In Volume LM
LLV4 LLV3 LLV2 LLV1 LLV0
RLV[4:0] LLV[4:0] LM
Reg Name Num 12h
Right Line In Volume. Allows setting the Line In right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Left Line In Volume. Allows setting the Line In left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Line In Mute. When this bit is set to "1," the channel is muted.
CD Volume (Index 12h)
D15 D14 D13 X D12 D11 D10 D9 D9 D8 D8 D7 D7 X D6 D6 X D5 D5 X D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
CD Volume CVM X
LCV4 LCV3 LCV2 LCV1 LCV0
RCV4 RCV3 RCV2 RCV1 RCV0 8808h
RCV[4:0] LCV[4:0] CVM
Right CD Volume. Allows setting the CD right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Left CD Volume. Allows setting the CD left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. CD Volume Mute. When this bit is set to "1," the channel is muted.
-14-
REV. 0
AD1886A
Video Volume (Index 14h)
Reg Name Num 14h D15 D14 X D13 X D12 D11 D10 D9 D9 D8 D8 D7 D7 X D6 D6 X D5 D5 X D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
Video Volume VM VM
LVV4 LVV3 LVV2 LVV1 LVV0
RVV4 RVV3 RVV2 RVV1 RVV0 8808h
RVV[4:0] LVV[4:0] VM
Reg Name Num 16h Aux Volume
Right Video Volume. Allows setting the Video right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Left Video Volume. Allows setting the Video left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Video Mute. When this bit is set to "1," the channel is muted.
AUX Volume (Index 16h)
D15 AM AM D14 X D13 X D12 D11 D10 D9 D9 D8 D8 D7 D7 X D6 D6 X D5 D5 X D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
LAV4 LAV3 LAV2 LAV1 LAV0
RAV4 RAV3 RAV2 RAV1 RAV0 8808h
RAV[4:0] LAV[4:0] AM
Reg Name Num 18h PCM Out Volume
Right Aux Volume. Allows setting the Aux right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Left Aux Volume. Allows setting the Aux left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Aux Mute. When this bit is set to "1," the channel is muted.
PCM Out Volume (Index 18h)
D15 OM OM D14 X D13 X D12 D11 D10 D9 D9 D8 D8 D7 D7 X D6 D6 X D5 D5 X D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
LOV4 LOV3 LOV2 LOV1 LOV0
ROV4 ROV3 ROV2 ROV1 ROV0 8808h
ROV[4:0] LOV[4:0] OM
Right PCM Out Volume. Allows setting the PCM right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Left PCM Out Volume. Allows setting the PCM left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. PCM Out Volume Mute. When this bit is set to "1," the channel is muted.
Volume Table (Index 0Ch to 18h)
Mute 0 0 0 1
x4 . . . x0 00000 01000 11111 xxxxx
Function +12 dB Gain 0 dB Gain -34.5 dB Gain - dB Gain
REV. 0
-15-
AD1886A
Record Select Control Register (Index 1Ah)
Reg Name Num 1Ah D15 D14 X D13 X D12 X D11 X D10 LS2 D9 D9 LS1 D8 D8 LS0 D7 D7 X D6 D6 X D5 D5 X D4 D4 X D3 D3 X D2 D2 RS2 D1 D1 RS1 D0 D0 RS0 Default 0000h
Record Select X
RS[2:0] LS[2:0]
Right Record Select Left Record Select
Used to select the record source independently for right and left. See table for legend. The default value is 0000h, which corresponds to Mic in. RS2 . . . RS0 0 1 2 3 4 5 6 7 Right Record Source MIC CD_R VIDEO_R AUX_R LINE_IN_R Stereo Mix (R) Mono Mix PHONE_IN
LS2 . . . LS0 0 1 2 3 4 5 6 7
Record Gain (Index 1Ch)
Reg Name Num 1Ch Record Gain D15 IM IM D14 X D13 X D12 X D11 LIM3 D10 LIM2 D9 D9
Left Record Source MIC CD_L VIDEO_L AUX_L LINE_IN_L Stereo Mix (L) Mono Mix PHONE_IN
D8 D8 LIM0
D7 D7 X
D6 D6 X
D5 D5 X
D4 D4 X
D3 D3 RIM3
D2 D2 RIM2
D1 D1 RIM1
D0 D0 RIM0
Default 8000h
LIM1
RIM[3:0] LIM[3:0] IM
Right Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB and the range is 0 dB to +22.5 dB. Left Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB and the range is 0 dB to +22.5 dB. Input Mute 0 = Unmuted 1 = Muted or - dB Gain IM 0 0 1 xIM3 . . . xIM0 1111 0000 xxxxx Function +22.5 dB Gain 0 dB Gain - dB Gain
-16-
REV. 0
AD1886A
General-Purpose Register (Index 20h)
Reg Num Name 20h D15 D14 D13 3D 3D D12 X D11 X D10 X D9 D9 MIX D8 D8 MS MS D7 D7 D6 D6 D5 D5 X D4 D4 X D3 D3 X D2 D2 X D1 D1 X D0 D0 X Default X
General-Purpose POP X
LPBK X
Note: This register should be read before writing to generate a mask for only the bit(s) that need to be changed. The function default value is 0000h, which is all off. LPBK MS Loopback Control. ADC/DAC digital loopback mode. Mic Select 0 = Mic1 1 = Mic2 Mono Output Select 0 = Mix 1 = Mic 3D Phat Stereo Enhancement 0 = Phat Stereo is off. 1 = Phat Stereo is on. PCM Output Path and Mute. The POP bit controls the optional PCM out 3D bypass path (the pre and post 3D PCM out paths are mutually exclusive). 0 = pre 3D 1 = post 3D
MIX
3D
POP
3D Control Register (Index 22h)
Reg Name Num 22h 3D Control D15 X D14 X D13 X D12 X D11 X D10 X D9 D9 X D8 D8 X D7 D7 X D6 D6 X D5 D5 X D4 D4 X D3 D3 DP3 D2 D2 DP2 D1 D1 DP1 D0 D0 DP0 Default 0000h
DP[3:0]
Depth Control. Sets 3D "Depth" Phat Stereo enhancement according to table below. DP3 . . . DP0 0 1 * * 14 15 Depth 0% 6.67% * * 93.33% 100%
REV. 0
-17-
AD1886A
Subsection Ready Register (Index 26h)
Reg Name Num 26h D15 D14 PR6 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 X D5 D5 X D4 D4 X D3 D3 REF D2 D2 ANL D1 D1 D0 D0 Default
Power-Down Cntrl/Stat X
PR5 PR4 PR3 PR2 PR1 PR0 X
DAC ADC NA NA
Note: The ready bits are read only; writing to REF, ANL, DAC, ADC will have no effect. These bits indicate the status for the AD1886A subsections. If the bit is a one, that subsection is "ready." Ready is defined as the subsection able to perform in its nominal state. ADC DAC ANL REF PR[6:0] ADC section ready to transmit data. DAC section ready to accept data. Analog gainuators, attenuators, and mixers ready. Voltage References, VREF and VREFOUT up to nominal level. AD1886A Power-Down Modes. The first three bits are to be used individually rather than in combination with each other. The last bit, PR3, can be used in combination with PR2 or by itself. The mixer and reference cannot be powered down via PR3 unless the ADCs and DACs are also powered down. Nothing else can be powered up until the reference is up. PR0--Power-Down ADC PR1--Power-Down DAC PR2--Power-Down Analog Mixer PR3--Power-Down VREF and VREFOUT PR4--Power-Down AC-Link PR5--Power-Down Internal Clock PR6--Power-Down Headphone PR5 has no effect unless all ADCs, DACs, and the AC-Link are powered down. The reference and the mixer can be either up or down, but all power-up sequences must be allowed to run to completion before PR5 and PR4 are both set. In multiple-codec systems, the master codec's PR5 and PR4 bits control the slave codec. PR5 is also effective in the slave codec if the master's PR5 bit is clear, but the PR4 bit has no effect except to enable or disable PR5. Power-Down State ADC Power-Down DAC Power-Down ADC and DAC Power-Down Mixer Power-Down ADC + Mixer Power-Down DAC + Mixer Power-Down ADC + DAC + Mixer Power-Down Standby PR6 0 0 0 0 0 0 0 1 PR5 0 0 0 0 0 0 0 1 PR4 0 0 0 0 0 0 0 1 PR3 0 0 0 0 0 0 0 1 PR2 0 0 0 1 1 1 1 1 PR1 0 1 1 0 0 1 1 1 PR0 1 0 1 0 1 0 1 1
Extended Audio ID Register (Index 28h)
Reg Name Num 28h Extended Audio ID D15 ID1 D14 ID0 D13 X D12 X D11 X D10 X D9 D9 X D8 D8 X D7 D7 X D6 D6 X D5 D5 X D4 D4 X D3 D3 X D2 D2 SPDF D1 D1 X D0 D0 VRA Default 0001h
Note: The Extended Audio ID is a read only register. VRA SPDF ID[1:0] Variable Rate Audio. VRA = 1 indicates support for Variable Rate Audio. "1" indicates SPDIF support, "0" indicates no SPDIF support. ID1, ID0 is a 2-bit field which indicates the codec configuration.
-18-
REV. 0
AD1886A
Extended Audio Status and Control Register (Index 2Ah)
Reg Name Num 2Ah D15 D14 D13 D12 D11 D10 X X X X D9 D9 D8 D8 X D7 D7 X D6 D6 X D5 D5 SPSA1 D4 D4 SPSA0 D3 D3 X D2 D2 D1 D1 D0 D0 VRA Default 0000h
Ext'd Audio Stat/Ctrl X
SPCV X
SPDIF X
Note: The Extended Audio Status and Control Register is a read/write register that provides status and control of the extended audio features. VRA SPDIF SPSA[1,0] Variable Rate Audio. VRA = 1 enables Variable Rate Audio mode (sample rate control registers and SLOTREQ signaling. SPDIF transmitter subsystem enable/disable bit: "1" indicates SPDIF is enabled, "0" indicates SPDIF is disabled. SPDIF Slot Assignment: SPSA[1, 0] = 00 SPDIF uses AC-LINK slots 3 and 4. SPSA[1, 0] = 01 SPDIF uses AC-LINK slots 7 and 8. SPSA[1, 0] = 10 SPDIF uses AC-LINK slots 6 and 9. SPSA[1, 0] = 11 Reserved. SPDIF Configuration Valid: (Read Only) "1" indicates current SPDIF configuration (SPA, SPR, DAC-Rate) is supported. "0" indicates current SPDIF configuration (SPA, SPR, DAC-Rate) is not supported.
SPCV
PCM DAC Rate Register (Index 2Ch)
Reg Num Name D15 SR15 D14 SR14 D13 SR13 D12 SR12 D11 SR11 D10 SR10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
2Ch/(7Ah) PCM DAC Rate
SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h
Note: 2Ch is an alias for 7Ah. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA, both sample rates are reset to 48 kHz. SR[15:0] Writing to this register allows programming of the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (bb80h) causes the codec to saturate. For all rates, if the value written to the register is supported, that value will be echoed back when read; otherwise, the closest rate supported is returned.
PCM ADC Rate Register (Index 32h)
Reg Num 32h/(78h) Name PCM ADC Rate D15 SR15 D14 SR14 D13 SR13 D12 SR12 D11 SR11 D10 SR10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h
Note: 32h is an alias for 78h. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA then both sample rates are reset to 48 kHz. SR[15:0] Writing to this register allows programming of the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (bb80h) causes the codec to saturate. For all rates, if the value written to the register is supported, that value will be echoed back when read; otherwise, the closest rate supported is returned.
REV. 0
-19-
AD1886A
SPDIF Control Register (Index 3Ah)
Reg Name Num 3Ah D15 D14 D13 X D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
SPDIF Control V
SPSR1 SPSR0 L
CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE
COPY AUD PRO 0000h
Note: Register 3Ah is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or subframe in the V case). With the exception of V, this register should only be written to when the SPDIF transmitter is disabled (SPDIF bit in register 2Ah is "0"). This ensures that control and status information startup correctly at the beginning of SPDIF transmission. PRO AUD COPY PRE CC[6-0] L SPSR[1,0] Professional: "1" indicates Professional use of channel status, "0" Consumer. Non-Audio: "1" indicates data is non PCM format, "0" data is PCM. Copyright: "1" indicates copyright is not asserted, "0" copyright is asserted. Preemphasis: "1" indicates filter preemphasis is 50/15 s, "0" preemphasis is none. Category Code: Programmed according to IEC standards, or as appropriate. Generation Level: Programmed according to IEC standards, or as appropriate. SPDIF Transmit Sample Rate: SPSR[1:0] = "00" Transmit Sample Rate = 44.1 kHz. SPSR[1:0] = "01" Reserved. SPSR[1:0] = "10" Transmit Sample Rate = 48 kHz. SPSR[1:0] = "11" Transmit Sample Rate = 32 kHz. Validity: This bit affects the "Validity flag," bit <28> transmitted in each subframe and enables the SPDIF transmitter to maintain connection during error or mute conditions. V = 1 Each SPDIF subframe (L + R) has bit <28> set to "1." This tags both samples as valid. V = 0 Each SPDIF subframe (L + R) has bit <28> set to "0" for valid data and "1" for invalid data (error condition).
V
Jack Sense/SPDIF Register (Index 72h)
Reg Num 72h N ame D 15 D 14 D 13 D 12 D 11 X D 10 JSO E D9 D9 JSLM D8 D8 JSD D7 D7 X D6 D6 JSC D5 D5 JSM M D4 D4 D3 D3 D2 D2 X D1 D0 D1 D0 X D efau lt
Ja c k Se n se / SP D IF SP M IX JS0 D
SPRZ JSPD
JSM VW 1
JS1 0000h
Note: All register bits are read/write except for JSI, JS and VWI, which are read only. JSI Indicates that Jack Sense pin has generated an interrupt. Must be enabled by JSM bit and remains set until software clears JSC bit. VWI Indicates Voice Wake Interrupt occurred. JSM Jack Sense Mode: 1 = Interrupt Mode (Software intervention required). 0 = Jack Sense Mode ( Hardware asserted Mono/Line Muting). JSMM Jack Sense Mono Mute: Setting this bit enables Jack Sense to mute the Mono output. JSC Jack Sense Clear: Setting this bit clears the Jack Sense interrupt (only needed when JSM = 1). JSD Jack Sense Disabled: Setting this bit disables Jack Sense functionality. JSLM Jack Sense Line Mute: Setting this bit enables Jack Sense to mute the LINE_OUT output. JSOE Jack Sense Output Enable: Setting this bit allows the JS pin to operate as GPIO (output mode only). JSPD Jack Sense Pull-up Disable: Setting this bit disables the internal Jack Sense pull-up. JSOD Jack Sense Output Data: Data on this bit is transferred to the JS pin if JSOE = 1 (otherwise no effect). SPRZ 1 = SPDIF Return to Zero on under run. 0 = SPDIF Repeat last sample on under run. SPMIX 1 = SPDIF Transmits output of ADC. 0 = SPDIF Transmits AC-Link Time Slot Data.
-20-
REV. 0
AD1886A
Serial Configuration (Index 74h)
Reg Name Num 74h D15 D14 D13 D12 D11 D10 D9 D9 X D8 D8 D7 D6 D7 D6 X X D5 D4 D5 D4 X X D3 D3 X D2 D2 X D1 D1 X D0 Default D0 X X
Serial SLOT REGM2 REGM1 REGM0 X Configuration 16 16
DHWR X
Note: This register is not reset when the reset register (Register 00h) is written. DHWR REGM0 REGM1 REGM2 SLOT16 Disable Hardware Reset Master Codec Register Mask Slave 1 Codec Register Mask Slave 2 Codec Register Mask Enable 16-bit slots.
If your system uses only a single AD1886A, you can ignore the register mask bits. SLOT16 makes all AC Link slots 16 bits in length, formatted into 16 slots.
Miscellaneous Control Bits (Index 76h)
Reg Num 76h Name D15 D14 D13 D12 D11 D10 D9 D8 D9 D8 D7 D7 D6 D6 D5 D5 D4 D3 D2 D4 D3 D2 D1 D0 D1 D0 Default
DAC LPMI Misc Control Bits Z X X
DAM DMS DLSR X
MOD ALSR EN EN
SRX10 SRX8 D7 D7 D7 D7 X
X
DRSR X
ARSR 0000h
ARSR
ADC Right Sample Generator Select 0 = SR0 Selected (32h) 1 = SR1 Selected (2Ch) DAC Right Sample Generator Select 0 = SR0 Selected (32h) 1 = SR1 Selected (2Ch) Multiply SR1 rate by 8/7 Multiply SR1 rate by 10/7. SRX10D7 and SRX8D7 are mutually exclusive; SRX10D7 has priority if both are set. Modem filter enable (left channel only). Change only when DACs are powered down. ADC Left Sample Generator Select 0 = SR0 Selected (32h) 1 = SR1 Selected (2Ch) DAC Left Sample Generator Select 0 = SR0 Selected (32h) 1 = SR1 Selected (2Ch) Digital Mono Select 0 = Mixer 1 = Left DAC + Right DAC Digital Audio Mode. DAC Outputs bypass analog mixer and sent directly to the codec output. Low-Power Mixer Zero-fill (vs. repeat) if DAC is starved for data.
DRSR
SRX8D7 SRX10D7 MODEN ALSR
DLSR
DMS
DAM LPMIX DACZ
REV. 0
-21-
AD1886A
Sample Rate 0 (Index 78h)
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D2 D2 D1 D1 D0 D0 Default
(32h)/78h Sample Rate 0 SR015 SR014 SR013 SR012 SR011 SR010 SR09 SR08 SR07 SR06 SR05 SR04 SR03 SR02 SR01 SR00 BB80h
Note: 32h is an alias for 78h. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA then both sample rates are reset to 48 kHz. SR0[15:0] Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hertz increments. Programming a value greater than 48 kHz or less than 7 kHz may cause unpredictable results.
Sample Rate 1 (Index 7Ah)
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D2 D2 D1 D1 D0 D0 Default
(2Ch)/7Ah Sample Rate 1 SR115 SR114 SR113 SR112 SR111 SR110 SR19 SR18 SR17 SR16 SR15 SR14 SR13 SR12 SR11 SR10 BB80h
Note: 2Ch is an alias for 7Ah. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA then both sample rates are reset to 48 kHz. SR1[15:0] Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hertz increments. Programming a value greater than 48 kHz or less than 7 kHz may cause unpredictable results.
Vendor ID1 Register (Index 7Ch)
Reg Name Num 7Ch Vendor ID1 D15 F7 F7 D14 F6 F6 D13 F5 F5 D12 F4 F4 D11 F3 F3 D10 F2 F2 D9 D9 F1 F1 D8 D8 F0 F0 D7 D7 S7 S7 D6 D6 S6 S6 D5 D5 S5 S5 D4 D4 S4 S4 D3 D3 S3 S3 D2 D2 S2 S2 D1 D1 S1 S1 D0 D0 S0 S0 Default 4144h
S[7:0] F[7:0]
This register is ASCII encoded to `A.' This register is ASCII encoded to `D.'
Vendor ID2 Register (Index 7Eh)
Reg Num 7Eh Name Vendor ID2 D15 T7 T7 D14 T6 T6 D13 T5 T5 D12 T4 T4 D11 T3 T3 D10 T2 T2 D9 D9 T1 T1 D8 D8 T0 T0 D7 D7 REV7 D6 D6 REV6 D5 D5 REV5 D4 D4 REV4 D3 D3 REV3 D2 D2 REV2 D1 D1 REV1 D0 D0 REV0 Default 5363h
T[7:0]
This register is ASCII encoded to `S.'
-22-
REV. 0
AD1886A
AVDD NOTE IF NOT USED, GROUND JACK SENSE PIN. (PIN 47) NC NC
0.1 F NC
+ 10 F
DVDD
48 47 46 45 44 43 42 SPDIF JS ID1 ID0 AVSS3 AVDD3
U1
10 F 22pF 0.1 F 0.1 F
24.576MHz 22pF
1 2 3 4 5 6 7 8 9 10 11 12
NC HP_OUT_R AVSS2 HP_OUT_L AVDD2 MONO_OUT
41 40 39 38 37
DVDD1 XTL_IN XTL_OUT DVSS1 SDATA_OUT BIT_CLK DVSS2 SDATA_IN DVDD2 SYNC RESET PC_BEEP
AD1886A
LINE_OUT_R LINE_OUT_L CX3D RX3D FILT_L FILT_R AFILT2 AFILT1 VREFOUT VREF AVSS1 AVDD1
SDATA_OUT SDATA_IN SYNC RESET 47 BIT_CLK 47pF
PHONE_IN AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND_REF CD_R MIC1 MIC2 LINE_IN_L LINE_IN_R
36 35 34 33 32 31 30 29 28 27 26 25
0.1 F 47nF 1F + 270pF NPO
1F +
270pF NPO
+ 0.1 F 10 F
0.1 F
13 14 15 16 17 18
19 20 21 22 23 24
AVDD
NC = NO CONNECT FB 600Z NOTE ALL UNUSED ANALOG INPUTS (LINE_IN_L/R, VIDEO_L/R, MIC1, MIC2, PC_BEEP, PHONE_IN, AND CD_L/R/GND) MUST BE LEFT UNCONNECTED.
Figure 9. Recommended Power Connections, Decoupling and Support Components
SPDIF TRANSMITTER OUTPUT CONNECTION
The codec SPDIF output is located on Pin 48. This pin has a weak internal pull-up that allows detection of SPDIF connector hardware at power-up and automatically enables or disables the SPDIF transmitter. This feature allows system manufacturers to populate or depopulate SPDIF connector hardware according to their requirements. When the output pin is simply left open (NC) or strapped high by a pull-up resistor, the internal sense circuitry disables the SPDIF transmitter. This condition prevents the SPDIF enable bit on Register 2Ah from being enabled. When the output pin is strapped low by a pull-down resistor (10 k or less), the SPDIF transmitter is enabled and the SPDIF enable bit on Register 2Ah can be asserted. The following circuits (Figure 10 and Figure 11) describe two ways to provide an SPDIF connection to the codec.
SPDIF OUT (CODEC PIN 48) U1 R2 10k 4 3 R1 8.2k C1 0.1 F 2 1 NC INPUT VCC LED GND 6 SPDIF OUT (CODEC PIN 48) 1 R3 10k 2 R2 240 R2 110 1 T1 J1 RCA JACK 5 5
5V (LOGIC)
U1A
NC
3.3V BUFFER (CAPABLE OF 12mA DRIVE)
4 1:1
8
TOTX173 TOSLINK
NC = NO CONNECT
Figure 10. SPDIF Output Connection Using Optical Link
Figure 11. SPDIF Output Connection Using Electrical Link
REV. 0
-23-
AD1886A
The first option consists of an optical link using a TOSLINK fiber-optic transmitting module. A typical offering is the TOSHIBA TOTX173 module for PCB mounted applications. This module can drive fiber optic cables up to 10 meters long, depending on the cable hardware used. This solution offers compatibility with state of the art audio systems and provides excellent common-mode rejection and noise immunity. R1 sets the current level for the internal LED and R2 allows the SPDIF transmitter to be enabled at power-up. Note that the TOSLINK module requires VCC = 5 V (PC logic supply). The second method uses an electrical connection matching the requirements of the IEC958 "Digital Audio Interface" for consumer products. This method uses a 75 coax cable as the connecting medium, with RCA type connectors at both ends. The transmission distance is at least 10 to 15 meters depending on the hardware used. The nominal electrical levels are 0.5 V p-p with a required bandwidth of 7 MHz. The 1:1 ratio transformer is used for galvanic isolation and for improved common-mode noise rejection. R1 and R2 provide the proper signal amplitude and impedance matching. R3 allows the SPDIF transmitter to be enabled at power-up.
JACK SENSE OPERATION
The AD1886A features a Jack Sense pin (JS) that can be used with the HP_OUT or LINE_OUT jacks to automatically mute the other audio outputs. When the Jack Sense pin is connected to one of the output jacks, the AD1886A can sense whether an audio plug has been inserted into the jack and automatically mute the LINE_OUT or MONO_OUT or both outputs. The JS pin should normally be connected to the HP_OUT jack to automatically mute the MONO_OUT and LINE_OUT audio signals, alternatively the JS pin can be connected to the LINE_OUT jack to automatically mute the MONO_OUT signal. The action of the JS pin can be programmed by setting the JSLM and JSMM bits in the Jack Sense Register (72h). The following table summarizes the Jack Sense operation:
Table I. Jack Sense Operation Table
JSLM Bit (Reg 72h, D9 Bit) 1 1 0 0
JSMM Bit (Reg 72h, D5 Bit) 1 0 1 0
JS State = HIGH (PLUG INSERTED) LINE_OUT = ON MONO_OUT = ON LINE_OUT = ON MONO_OUT = MUTE LINE_OUT = MUTE MONO_OUT = ON LINE_OUT = MUTE MONO_OUT = MUTE
JS State = LOW (PLUG REMOVED) LINE_OUT = ON MONO_OUT = ON LINE_OUT = ON MONO_OUT = ON LINE_OUT = ON MONO_OUT = ON LINE_OUT = ON MONO_OUT = ON
The Jack Sense functionality is enabled by default on codec power-up (JSD bit = 0), however the JSLM and JSMM bits are set to zero, therefore the muting action is not enabled for both outputs. The JSLM and JSMM bits have to be configured by the software or INF configuration file for the desired muting action. The Jack Sense pin is active high and contains an active internal pull-up. If the Jack Sense input is not going to be used, it should be pulled down to digital ground using 10 k resistors.
-24-
REV. 0
AD1886A
CONNECTING THE JACK SENSE TO THE OUTPUT JACKS Headphone Jack
The diagram on Figure 12 shows the preferred method to connect the Jack Sense line to the HP_OUT jack. This scheme requires a stereo jack with a normally closed and isolated single switch. The switch holds the Jack Sense line low (grounded) until an audio plug is inserted, causing the switch to open and the Jack Sense line to go high due to the codec internal pull-up. The R2 and R3 resistors keep the electrolytic output caps properly polarized while the HP_OUT jack is not used.
NOTE: LOCATE R1 CLOSE TO CODEC. R1 2k JACK SENSE LINE
TO CODEC JS (PIN 47)
C2 220 F FROM CODEC HP_OUT_R (PIN 41) + C3 220 F FROM CODEC HP_OUT_L (PIN 39) + R3 10k R2 10k
OPTIONAL EMC COMPONENTS L1 600Z 5 4 3 2 1
ISOLATED NC SWITCH
L2 600Z C1 470pF C4 470pF
HEADPHONE OUT
Figure 12. Jack Sense Connection to HP_OUT Jack, Using Isolated Switch
Alternatively, when an audio output jack containing an isolated switch is not available, the circuit shown in Figure 13 can be used. While the audio plug is out, this circuit keeps the Jack Sense line state low, by the pull-down effect of R2 (with no audio present) or by tracking the lower peaks of the HP_OUT audio signal. Once an audio plug is inserted and the jack switch opens, the Jack Sense line switches to a high state due to the codec internal pull-up, which quickly charges C1 to DVDD. The R2 and R3 resistors also keep the electrolytic output caps properly polarized while the HP_OUT jack is not used.
NOTE: LOCATE R1 AND C1 CLOSE TO CODEC. JACK SENSE R1 2k TO CODEC JS (PIN 47) C1 2F CERAMIC D1 MMBD914 OPTIONAL EMC COMPONENTS C2 220 F FROM CODEC HP_OUT_R (PIN 41) + C3 220 F FROM CODEC HP_OUT_L (PIN 39) + R3 10k C5 470pF R2 10k C4 470pF L2 600Z L1 600Z 1 2 3 4 5 J1
HEADPHONE OUT
Figure 13. Jack Sense Connection to HP_OUT Jack, Using Nonisolated Switch
LINE OUT JACK
Although not shown, if a LINE_OUT jack is used and the Jack Sense functionality is desired with this jack, the LINE_OUT jack should be wired in a similar configuration as shown above for the HP_OUT jack (preferably Figure 12). We recommend that in this case the output coupling caps (C2, C3) be set to 2.2 F. All other values should be kept the same.
REV. 0
-25-
AD1886A
APPLICATION CIRCUITS
CD-ROM CONNECTIONS
Typical CD-ROM drives generate 2 V rms output and require a voltage divider for compatibility with the Codec input (1 V rms range). The recommended circuit is a group of divide-by-two voltage dividers as shown on Figure 14. The CD_GND_REF pin is used to cancel differential ground noise from the CD-ROM. For optimal noise cancellation, this section of the divider should have approximately half the impedance of the Right and Left channel section dividers.
VOLTAGE DIVIDER R1 4.7k R2 4.7k HEADER FOR CD ROM AUDIO (LGGR) 1 2 3 4 R3 2.7k R4 2.7k R5 4.7k R6 4.7k AC-COUPLING C1 0.33 F + TO CODEC CD_L INPUT
C2 0.33 F + TO CODEC CD_GND_REF INPUT
C3 0.33 F + TO CODEC CD_R INPUT
Figure 14. Typical CD-ROM Audio Connections
LINE_IN, AUX, AND VIDEO INPUT CONNECTIONS
Most audio sources also generate 2 V rms audio level and require a -6 dB input voltage divider to be compatible with the Codec inputs. Figure 15 shows the recommended application circuit. For applications requiring EMC compliance, the EMC components should be configured and selected to provide adequate RF immunity and emissions control.
EMC COMPONENTS LINE/AUX/VIDEO INPUT J1 1 2 3 4 5 L2 600Z C1 470pF L1 600Z C2 470pF R3 4.7k R4 4.7k VOLTAGE DIVIDER R1 4.7k R2 4.7k AC-COUPLING C3 0.33 F + TO CODEC RIGHT CHANNEL INPUT
C4 0.33 F + TO CODEC LEFT CHANNEL INPUT
Figure 15. LINE_IN, AUX and VIDEO Input Connections
MICROPHONE CONNECTIONS
The AD1886A contains an internal microphone preamp with 20 dB gain; in most cases a direct microphone connection as shown in Figure 16 is adequate. If the microphone level is too low, an external preamp can be added as shown in Figure 17. In either case the microphone bias can be derived from the codec's internal reference (VREFOUT) using a 2.2 k resistor. For the preamp circuit, the VREFOUT signal can also provide the midpoint bias for the amplifier. To meet the PC99 1.0A requirements, the MIC signal should be placed on the microphone jack tip and the bias on the ring. This configuration supports electret microphones with three conductor plugs as well as dynamic microphones with two conductor plugs (ring and sleeve shorted together). Additional filtering may be required to limit the microphone response to the audio band of interest.
-26-
REV. 0
AD1886A
EMC COMPONENTS J1 1 2 3 4 5 MIC INPUT L1 600Z C2 470pF L2 600Z C1 470pF MIC BIAS R1 2.2k FROM CODEC VREFOUT AC-COUPLING C3 0.22 F TO CODEC MIC1 OR MIC2 INPUT
Figure 16. Recommended Microphone Input Connections
PREAMP EMC COMPONENTS J1 1 2 3 4 5 MIC INPUT L1 600Z C2 470pF L2 600Z C1 470pF MIC BIAS R1 2.2k AC-COUPLING C3 0.22 F R2 10k U1 AD8531 R3 100k AVDD
AC-COUPLING C4 0.22 F TO CODEC MIC1 OR MIC2 INPUT
FROM CODEC VREFOUT
Figure 17. Microphone with Additional External Preamp (20 dB Gain)
LINE OUTPUT CONNECTIONS
The AD1886A Codec provides stereo LINE_OUT signals at a standard 1 V rms level. These signals must be ac-coupled before they can be connected to an external load. After the ac-coupling, a minimal resistive load is recommended to keep the capacitors properly biased and reduce clicks and pops when plugging stereo equipment into the output jack. The capacitor values should be selected to provide a desired frequency response, taking into account the nominal impedance of the external load. To meet the PC99 specification for PCs, testing must be performed with a 10 k load, therefore a minimum of 1 F value is recommended to achieve less than -3 dB roll-off at 20 Hz.
STEREO LINE_OUT JACK J1 L2 600Z C1 470pF L1 600Z C2 470pF R1 47k R2 47k
C3 1F FROM CODEC LINE_OUT_R
FROM CODEC LINE_OUT_L C4 1F
Figure 18. Recommended LINE_OUT Connections
PC BEEP INPUT CONNECTIONS
The recommended PC BEEP input circuit is shown below. Under most cases the PC_BEEP signal should be attenuated, filtered and then ac-coupled into the Codec.
PC_BEEP (FROM ICH)
R1 10k C1 0.1 F
C2 0.1 F TO CODEC PC_BEEP INPUT R2 1k
Figure 19. Recommended PC_BEEP Connections
REV. 0
-27-
AD1886A
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead Thin Plastic Quad Flatpack (LQFP) (ST-48)
0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45)
0.354 (9.00) BSC SQ
48 1 37 36
TOP VIEW
(PINS DOWN)
0.276 (7.00) BSC SQ
25
COPLANARITY 0.003 (0.08) 0.008 (0.2) 0.004 (0.09)
0 MIN
12 13 24
0.019 (0.5) 0.011 (0.27) BSC 0.006 (0.17) 7 0 0.006 (0.15) SEATING 0.002 (0.05) PLANE 0.057 (1.45) 0.053 (1.35)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
-28-
REV. 0
PRINTED IN U.S.A.
C02411-0-10/01(0)

▲Up To Search▲

Price & Availability of AD1886

	To Download AD1886 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .